Flash memory cells are often fabricated on the same substrate with logic or linear transistors. In order to have an efficient manufacturing process, the transistors for the control gate in the flash memory cells and the logic and linear transistors often share the same polysilicon mask. They also share the same sidewall oxidation process and the same reactive ion etch (RIE) of the gate. While the sharing of common steps is efficient, it also presents one or more technical problems. As features sizes shrink, logic and/or linear transistors require ultra shallow source and drain junction formation to avoid short channel effect (SCE). In order to achieve such ultra shallow source and drain junction formation the thermal budget for manufacturing the device must be kept very low. As such, sidewall oxidation process must be carried out at a low temperature or be entirely dispensed with. However, flash memory cell requires significant rounding of the gate edge to reduce the high electric fields that arise from the sharp gate edge, in order to retain charge in the gate stack. Gate rounding reduces leakage current by reducing the electric field around the charged trapped in the floating gate.